Page - 189 - in Photovoltaic Materials and Electronic Devices

andothervolatilecompoundsprior to theGaAsdeposition. Thegrowthbeganby depositing 0.25µm n+ doped GaAs layer at 530 ˝C followed by 1µm of n doped GaAs layer at 580 ˝C. Forty layers of 0.7 nm nominal thickness InAs QDs capped first by 5 nm In0.13Ga0.87As and then 7 nm GaAs spacer layer were subsequently deposited at 500 ˝C. Finally, 0.5µm p doped GaAs was grown at 580 ˝C followed by 0.1µm of p+ doped GaAs layer at 530˝C. The growth rate was: 0.24 Ås´1 for the InAs,2.22Ås´1 for the InGaAsand1.98Ås´1 forGaAs. Tworeferencepin-GaAsdiodeswithoutQDshavealsobeenfabricatedunder the same conditions either on nanostructured Si substrate and GaAs substrate. A schematic presentation of the pin-GaAs diode on Si substrate with and without QDs isgiven inFigure1. The sample was then etched in NaOH solution to break up the porous silicon layer and produce the structuration of the surface. Indeed, after the chemical dissolution of silicon skeleton, the rugged surface will be exposed to beam epitaxy. Additional details concerning the process as well as the morphological properties of the nanostructured Si surface and its impact on the quality of GaAs material grown on such Si surface can be found elsewhere [27]. After surface preparation, a cleaning and out gassing process of the silicon substrate was performed under vacuum condition in an introductory chamber with a rest pressure of 10−9 Torr at high temperature (760 °C), to remove the native oxide and other volatile compounds prior to the GaAs deposition. The growth began by depositing 0.25 µm n+ doped GaAs layer at 530 °C followed by 1 µm of n doped GaAs layer at 580 °C. Forty layers of 0.7 nm nominal thickness InAs QDs capped first by 5 nm In0.13Ga0.87As and then 7 nm GaAs spacer layer were subsequently deposited at 500 °C. Finally, 0.5 µm p doped GaAs was grown at 580 °C followed by 0.1 µm of p+ doped GaAs layer at 530 °C. The growth rate was: 0.24 Ås−1 for the InAs, 2.22 Ås−1 for the InGaAs and 1.98 Ås−1 for GaAs. Two reference pin-GaAs diodes without QDs have also been fabricated under the same conditions either on nanostructured Si substrate and GaAs substrate. A schematic presentation of the pin-GaAs diode on Si substrate with and without QDs is given in Figure 1. Figure 1. Schematic presentation of the investigated samples. (a) pin-GaAs/Si; (b) pin-GaAs/Si containing 40 QD layers. During the growth process, the surface morphology was in-situ monitored by reflection high-energy electron diffraction (RHEED). As shown by Figure 2, the RHEED pattern changed from streaky (Figure 2a) during the GaAs deposition, which is characteristic of 2D growth mode to a spotty pattern (Figure 2b) after the deposition of InAs material. The observed changes in the diffraction pattern represent the transition from 2D to 3D growth mode, testifying the QDs’ formation. Figure 1. Schematic presentation of the investigated samples. (a) pin-GaAs/Si; (b)pin-GaAs/Sicontaining40QDlayers. Duringthegrowthprocess, thesurfacemorphologywas in-situmonitoredby reflection high-energy electron diffraction (RHEED). As shown by Figure 2, the RHEEDpatternchangedfromstreaky(Figure2a)duringtheGaAsdeposition,which ischaracteristicof2Dgrowthmodetoaspottypattern(Figure2b)afterthedeposition of InAs material. The observed changes in the diffraction pattern represent the transitionfrom2Dto3Dgrowthmode, testifyingtheQDs’ formation. 189